1. Field
Example embodiments relate to a non-volatile memory device. Other example embodiments relate to a variable resistance non-volatile memory device having a storage node-diode structure formed using a buffer layer and a variable resistance material layer. Example embodiments relate to a variable resistance non-volatile memory device having with a less complex structure, a more stable switching property and capable of operating without additional switching devices (e.g., a diode or a transistor).
2. Description of the Related Art
Generally, a semiconductor memory device includes a plurality of unit memory cells connected to each other using circuits. In a dynamic random access memory (DRAM), a unit memory cell generally includes a switch and a capacitor. The DRAM may be highly integrated and operate fast. If the power is turned off, then the data stored in the DRAM is deleted.
Non-volatile memory devices (e.g., flash memories) retain stored data after the power is turned off. Flash memories have a low integration degree. Flash memories operate slower than DRAMs.
In the field of non-volatile memory devices, research is being performed on Magnetic Random Access Memories (MRAMs), Ferroelectric Random Access Memories (FRAMs), Phase-change Random Access Memories (PRAMs) and Resistance Random Access Memories (RRAMs). MRAMs, FRAMs, PRAMs and RRAMs include a storage node storing data and a transistor or a diode for driving the storage node.
FIG. 1 is a diagram illustrating a cross-sectional view of a conventional RRAM device including a storage node having a conventional variable resistance material and a diode. RRAMs have a variable resistance characteristic wherein resistance varies according to voltage similar to a transition metal oxide.
In a conventional RRAM device, the variable resistance material may be a material having different resistances with respect to the same applied voltage (e.g., a transition metal oxide (TMO)). Some examples of TMOs include zinc oxide (ZnO), titanium oxide (TiO2), niobium oxide (Nb2O5), zirconium oxide (ZrO2) and nickel oxide (NiO).
Referring to FIG. 1, a diode structure 10 including an n-type oxide layer 12 and a p-type oxide layer 13 is formed on the lower electrode 11. A central electrode 14, a variable resistance material layer 16 and an upper electrode 17 are sequentially formed on the diode structure 10. A buffer layer 15 may be between the central electrode 14 and the variable resistance material layer 16.
Several deposition processes and etching processes are performed in order to form a cross-point array structure from the conventional memory device as shown in FIG. 1. As such, the fabrication process may be complex and/or may increase the size of the memory device, reducing the degree of integration the device.